1. Field of the Invention
This invention relates to semiconductor memory and to methods and circuits for storing data in semiconductor memory at addresses selected to reduce the noticeable effects of defects and to memory with built-in security against unauthorized access of stored data.
2. Description of Related Art
Some semiconductor memory systems can record and playback continuous analog signals such as audio or image signals. In such systems, a recording process takes samples (i.e., instantaneous measurements of the level) of an analog signal to generate a data sequence that the semiconductor memory stores.
Depending on the type of memory, each sample is stored in digital form with one or more bits per memory cell or in analog form with one sample per memory cell. Such memory systems often include an address counter which indicates an address for storage of a sample in a data sequence. The address counter increments the address each time a sample is written so that samples are written at consecutive addresses. To play or recreate the recorded analog signal, the data sequence is read from the semiconductor memory in the sequential order of the recording, and samples read are sequentially converted to levels in an output signal.
Generally, a semiconductor memory includes an array of memory cells arranged in rows and columns and partitioned into independently addressable storage locations. Conventionally, each storage location corresponds to one or more memory cells in a row of the array. An address for a storage location identifies the row and the column associated with a memory cell in the storage location. Commonly, the most significant bits of an address form a row address that identifies the row containing the storage location, and the least significant bits of the address form a column address that identifies a column corresponding to one of the memory cells in the storage location. Often, when storing a sequence of samples to consecutive memory addresses, the column address is sequentially incremented, and the row address remains constant until the column address reaches the last position in the row. This fills a row of memory cells before starting writes to the next row.
For an audio recording and playback application, when a row or large number of adjacent cells in a row are defective, the defective cells contain unpredictable or incorrect values; and during signal playback, noticeable deadtime, static, or signal distortion appears in the portion of the signal recorded in defective memory cells. If all or a large number of memory cells in a column are defective, an error occurs in the signal played back each time a sample is read from a storage location including a defective memory cell. A column error thus results in periodic errors in the played-back signal where the period of the errors depends on the time required to read samples from a row. The errors may cause a repeating "pop" or "click" in a played-back sound. Periodic errors are undesirable because the human ear is attuned to detect such noise.
To handle hard defects (i.e., defects that are detectable by testing), most memories include redundant rows and columns of memory cells with redundant decoding circuits. When a defective row, a defective column, a number of defective adjacent memory cells, or even a single defective memory cell is detected during testing of a memory IC, a redundant row or column can be activated to replace the defective cells. Replacing defects in this manner increases memory cost because the redundant circuits increase integrated circuit area and because activation of the redundant circuits typically requires additional processing steps, such as laser programming during or after testing. Furthermore, a memory may still have latent defects or soft errors, which appear only after a specific period of operation of the memory. In the normal test flow, these defects typically cannot be detected as requiring replacement. Methods and circuits are thus sought to handle defects in semiconductor memory and record-and-playback systems and avoid lengthy disruptions or periodic errors that result from memory array defects.